GR716 Support
GR716 Microcontroller
DMON supports the GR716 microcontroller from Cobham-Gaisler. This microcontroller features a fault-tolerant LEON3 SPARC V8 processor, communication interfaces and on-chip ADC, DAC, Power-on-Reset, Oscillator, Brown-out detection, LVDS transceivers, regulators to support for single 3.3V supply, ideally suited for space and other high-rel applications. A block diagram of the GR716 is shown below. DMON provides support for all the functional units on the microcontroller. The sections below provide more information on DMON support for some specific functional units of the microcontroller.
Credit: GR716 User Manual Version 1.26
Startup Options
The table below shows GR716 startup options.
Command | Description |
---|---|
-iomx set [configName configName ...] | Set IOMX configurations for Device or Array of Devices (see IO switch matrix section below) |
-grcg or grcg_(index) [enable|disable][all|bit..bitN] | Enable|Disable all, single bit or array of bits for GRCLKGATE_(DeviceIndex) (see clock gating section below) |
Typical startup options used with the GR716 Mini development board are
-gui -u -baud 230400 -iomx set mem_gr716_mini_cfg0 -grcg enable 0x4 16 -nosram_1
Layout window
DMON represents the GR716 SOC in the layout below. By clicking on a functional block it's IP and register definitions are displayed in separate windows.
REX support
DMON supports the 16 bit REX instruction set.
DMON Functions View of loaded image (REX functions are marked with (REX))
Instruction Trace Information
DMON > inst 40 Rex Time Address Instruction Result R 00000008763 3100A170 ld [%i2 + 0x8], %l6 (rld [%i2 + 0x8], %l6) [0000000C] R 00000008765 3100A174 sub %l6, %i0, %l6 (rsub %i0, %l6) [00000000] R 00000008766 3100A176 cmp %l6, 0x0 (rcmp %l6, 0x0) [00000000] R 00000008767 3100A178 add %i5, %i0, %i5 (radd %i0, %i5) [3000005A] R 00000008768 3100A17A sub %i4, %i0, %i4 (rsub %i0, %i4) [00000000] R 00000008770 3100A17C st %l6, [%i2 + 0x8] (rst %l6, [%i2 + 0x8]) [3000FEB0][00000000] R 00000008771 3100A180 bne TestContinue_REX_0x31:__sfvwrite_r + 0x238 (rbne 0xffffff32) [00000000] R 00000008772 3100A182 add %g0, 0x0, %i0 (rset5 0x0, %i0) [00000000] R 00000008773 3100A184 ret (rretrest) [3100A181] R 00000008774 3100A184 restore %i7, 0x8, %g0 (rretrest) [31007E07] R 00000008777 31007E06 add %g0, %o0, %i0 (rmov %o0, %i0) [00000000] R 00000008778 31007E08 ba TestContinue_REX_0x31:__sprint_r + 0x74 (rba 0x48) [00000000] R 00000008781 31007E50 st %i4, [%i2 + 0x8] (rst %i4, [%i2 + 0x8]) [3000FEB0][00000000] R 00000008783 31007E54 st %i4, [%i2 + 0x4] (rst %i4, [%i2 + 0x4]) [3000FEAC][00000000] R 00000008784 31007E58 ret (rretrest) [31007E55] R 00000008785 31007E58 restore %i7, 0x8, %g0 (rretrest) [310042AB] R 00000008788 310042AA cmp %o0, 0x0 (rcmp %o0, 0x0) [00000000] R 00000008791 310042AC bne TestContinue_REX_0x31:_vfprintf_r + 0x29d0 (rbne 0x10) [00000000] R 00000008792 310042AE add %g0, 0x0, %i0 (rset5 0x0, %i0) [00000000] R 00000008793 310042B0 add %g0, 0xffffff24, %i2 (rset21 0xffffff24, %i2) [FFFFFF24] R 00000008794 310042B4 ld [%fp + %i2], %i1 (rld [%fp + %i2], %i1) [3000FEAC] R 00000008797 310042B8 st %i0, [%i1 + 0x0] (rst %i0, [%i1]) [3000FEAC][00000000] R 00000008798 310042BC add %g0, 0xfffffef8, %i0 (rset21 0xfffffef8, %i0) [FFFFFEF8] R 00000008800 310042C0 ldd [%fp + %i0], %i4 (rldd [%fp + %i0], %i4) [3000FED4][0000000C] R 00000008801 310042C4 ba TestContinue_REX_0x31:_vfprintf_r + 0x2a24 (rba 0x4e) [00000000] R 00000008804 31004312 ldub [%l6 + 0xd], %i0 (rldub [%l6 + 0xd], %i0) [00000089] R 00000008805 31004316 mov 0x40, %i1 (rone 0x6, %i1) [00000040] R 00000008806 31004318 and %i1, %i0, %i1 (rand %i0, %i1) [00000000] R 00000008807 3100431A cmp %i1, 0x0 (rcmp %i1, 0x0) [00000000] R 00000008810 3100431C bne TestContinue_REX_0x31:_vfprintf_r + 0x2a34 (rbne 0x6) [00000000] R 00000008811 3100431E add %g0, %i5, %i0 (rmov %i5, %i0) [0000000C] R 00000008812 31004320 ret (rretrest) [3100431D] R 00000008813 31004320 restore %i7, 0x8, %g0 (rretrest) [310018D1] R 00000008816 310018D0 add %g0, %o0, %i0 (rmov %o0, %i0) [0000000C] R 00000008817 310018D2 ret (rretrest) [310018CF] R 00000008818 310018D2 restore %i7, 0x8, %g0 (rretrest) [310012D1] R 00000008822 310012D0 st %o0, [%fp - 0xc] (rst %o0, [%fp - 12]) [3000FF94][0000000C] R 00000008823 310012D4 call TestContinue_REX_0x31:secondHello (call TestContinue_REX_0x31:secondHello) [310012D1] 00000008825 31001278 saverex %sp, %i0, %sp [3000FED0] R 00000008826 3100127C ta 0x1 (rset32 TestContinue_REX_0x31:watchData, %i0) [TRAPPED ]
REX Dissembled Instructions
DMON > coderex secondHello Address hex dis 0x31001278 9DE39F98 saverex %sp, %i0, %sp 0x3100127c A3E830000C7C rset32 TestContinue_REX_0x31:watchData, %i0 0x31001282 87EA30000C7C rld32 [TestContinue_REX_0x31:watchData], %o1 0x31001288 83E830000004 rset32 0x30000004, %o0 0x3100128e E0EE887C rst %i0, [%fp - 4] 0x31001292 40000181 call TestContinue_REX_0x31:printf 0x31001296 A23F rset5 0xffffffff, %i0 0x31001298 C4EE807C rld [%fp - 4], %o1 0x3100129c E101 rst %i0, [%o1] 0x3100129e 87E830000028 rset32 0x30000028, %o1 0x310012a4 C0EE8878 rst %o0, [%fp - 8] 0x310012a8 8101 rmov %o1, %o0 0x310012aa 8508 rmov %i0, %o1 0x310012ac 4000017A call TestContinue_REX_0x31:printf 0x310012b0 C0EE8874 rst %o0, [%fp - 12] 0x310012b4 83C0 rretrest 0x310012b6 00009DE3 unimp 0x9de3 0x310012b8 9DE39F98 saverex %sp, %i0, %sp 0x310012bc A220 rset5 0x0, %i0 0x310012be E0EE887C rst %i0, [%fp - 4] 0x310012c2 83E83000004E rset32 0x3000004E, %o0 0x310012c8 E0EE8878 rst %i0, [%fp - 8] 0x310012cc 40000172 call TestContinue_REX_0x31:printf 0x310012d0 C0EE8874 rst %o0, [%fp - 12] 0x310012d4 7FFFFFE9 call TestContinue_REX_0x31:secondHello 0x310012d8 E0EE8078 rld [%fp - 8], %i0 0x310012dc 83C0 rretrest
The table below shows GR716 REX commands:
Command | Description |
---|---|
rex [en|ill|tr]<cpuID> | Sets the REX mode(enable|illegal|transparent) for active cpu or cpuID if provided |
coderex [addr]<length> <force> | Disassemble REX instructions in memory. DMON will detect if address is in REX block and disassemble as REX. Force switch will bypass detection and disassemble as REX instruction |
breakrexs [addr]<cpuID> | Force to set REX Software break point. breaks command will scan if address is in REX block and set REX software break point |
DMA Controller
The GR716 microcontroller have 4 separate DMA controller with internal AHB/APB bridge units (GRDMAC). The GRDMAC units described in this section provides a flexible direct memory access controller. The core can perform burst transfers of data between AHB and APB peripherals at aligned or unaligned memory addresses.
One DMA channel per DMA controller is supported. The channel can be configured flexibly by means of two descriptor chains residing in main memory: a Memory to Buffer (M2B) chain and a Buffer to Memory (B2M) chain. Each chain is composed of a linked list of descriptors, where each descriptor specifies an AHB address and the size of the data to read/write, supporting a scatter/gather behavior.
DMON provides a number of specific tabs to allow the user to configure the GRDMAC registers, test DMA transfers, and load/save such test configurations. It is assumed that the user is familiar with the GRDMAC hardware.
GRDMAC status window
GRDMAC configuration window
GRDMAC descriptor configuration
GRDMAC waiting for trigger condition
GRDMAC and Descriptors status after trigger
Available commands for GRDMAC:
Command | Description |
---|---|
grdmac_0 b2m add [data|cond|econd] ch[N][addr] | Create B2M data|conditional|extended conditional descriptors at address for Channel |
grdmac_0 b2m remove [data|cond|econd] ch[N] [addr] | Remove B2M descriptor at address for Channel |
grdmac_0 core [en|dis] | Enable(Run) or Disable(Stop) GRDMAC Core |
grdmac_0 core reset | Reset GRDMAC Core to default values |
grdmac_0 ctrl ie [en|dis] | Global Interrupt Enable or Disable |
grdmac_0 ctrl iee [en|dis] | Interrupt Enable or Disable for Errors |
grdmac_0 ctrl me [en|dis] | Extended Mode Enable or Disable |
grdmac_0 ctrl ns [en|dis] | No Starve Mode Enable or Disable |
grdmac_0 ctrl sm [en|dis] | Simplified mode Enable or Disable |
grdmac_0 ctrl te [en|dis] | Timer Enable or Disable |
grdmac_0 ech [en|dis][all|ch# ch#+1] | Set Channel/Channels/All Channels Enabled/Disabled |
grdmac_0 ech [en|dis][ch#-ch#+n] | Set Channel Enabled or Disabled for Range of Channels |
grdmac_0 eirq [en|dis] | Set Interrupt enable for Errors (IEE) |
grdmac_0 error reset | Reset Error Register |
grdmac_0 irq [en|dis] | Set GRDMAC Global Interrupt Enable or Disable (IE) |
grdmac_0 irq [en|dis][all|ch# ch#+1] | Set Interrupt Mask for Channel/Channels/All Channels and Enable Global IRQ |
grdmac_0 irq [en|dis][ch#-ch#+n] | Set Interrupt Mask for Range of Channels and Enable Global IRQ |
grdmac_0 irq reset | Reset Interrupt Flag Register for all channels |
grdmac_0 load [file] | Load GRDMAC configurations from XML file |
grdmac_0 m2b add [data|cond|econd] ch[N] [addr] | Create M2B data|conditional|extended conditional descriptors at address for Channel |
grdmac_0 m2b remove [data|cond|econd] ch[N] [addr] | Remove M2B descriptor at address for Channel |
grdmac_0 save [file] | Save GRDMAC configuration to XML file |
grdmac_0 sbufdata | Display Internal Buffer Readout Area |
grdmac_0 scan | Scan M2B and B2M descriptor linked lists using Channel Vector Pointer |
grdmac_0 sdata [addr] | Print DMA data after successful B2M Descriptor at address |
grdmac_0 set cvp [value] | Set Channel Vector Pointer (CVP) |
grdmac_0 set trv [value] | Set Timer Reset Value (TIMER_RST) |
grdmac_0 status [offset] | Display GRDMAC core status of All registers or at offset (i.e.0x04) to the screen |
grdmac_0 tsl [0|32|64|128] | Set Transfer Size limit (TSL) |
DEMO
Basic GRDMAC Custom Configurations:
Debugging GRDMAC using DMON
Sample script:
memset write DLRAM_0_START 0x0 // Set Flag to 0 write 0x40000300 0x0 0x400 // Clear memory write 0x30000004 0xcafebabe 0x400 // Set Data to be transferred grdmac_0 core reset // Reset Core grdmac_0 load config.xml // Load GRDMAC and Descriptors configurations. Copy content of this File:CopyMeAndCreateXml.pdf and save as config.xml grdmac_0 core en // Start the core write DLRAM_0_START 0x1 // Set Flag to 1 to trigger data descriptor grdmac_0 sdata 0x40000120 // Output transferred data
IO Switch Matrix
The I/O switch matrix provides access to several I/O units. When an interface is not activated, its pins automatically become general purpose I/O. After reset, all I/O switch matrix pins are defined as inputs until programmed otherwise.
Configuration and assigning of functions to external I/O is flexible and is controlled by software via a set of registers.
DMON loads in configuration file iomx.config which located in DMON installation directory C:\Program Files (x86)\DMON\Local
User can modify all those configurations or create new custom that will be loaded when DMON starts.
Then, configuration can be applied using "iomx set name" command when DMON started or "-iomx set name" switch command at DMON initialization.
User can autocomplete configuration names using tab after "iomx set" or display all configurations starting with some combination of letters.
Command | Description |
---|---|
iomx set [configName configName ...] | Set IOMX configurations for Device or Array of Devices |
-iomx set [configName configName ...] | Switch to set IOMX configurations for Device or Array of Devices, when DMON starts |
iomx setpin [gpioN][val] | Set IOMX GPIO pin to value |
iomx show <all|configName> | Display all available IOMX configurations or Search by prefix |
iomx validate | Validate IOMX configurations |
iomx validate sample output:
DMON > iomx validate GPIO[00] mem_addr_0 GPIO[01] mem_addr_1 GPIO[02] mem_addr_2 GPIO[03] mem_addr_3 GPIO[04] mem_addr_4 GPIO[05] mem_addr_5 GPIO[06] mem_addr_6 GPIO[07] mem_addr_7 GPIO[08] mem_addr_8 GPIO[09] mem_addr_9 GPIO[10] mem_addr_10 GPIO[11] mem_addr_11 GPIO[12] mem_addr_12 GPIO[13] mem_addr_13 GPIO[14] mem_addr_14 GPIO[15] mem_addr_15 GPIO[16] mem_addr_16 GPIO[17] mem_addr_17 GPIO[18] mem_addr_18 GPIO[19] ram_csn_0 GPIO[20] gpio 20 GPIO[21] gpio 21 GPIO[22] gpio 22 GPIO[23] gpio 23 GPIO[24] gpio 24 GPIO[25] mem_data_0 GPIO[26] mem_data_1 GPIO[27] mem_data_2 GPIO[28] mem_data_3 GPIO[29] mem_data_4 GPIO[30] mem_data_5 GPIO[31] mem_data_6 GPIO[32] mem_data_7 GPIO[33] mem_oen GPIO[34] mem_wrn GPIO[35] gpio 35 GPIO[36] gpio 36 GPIO[37] gpio 37 GPIO[38] gpio 38 GPIO[39] gpio 39 GPIO[40] gpio 40 GPIO[41] gpio 41 GPIO[42] gpio 42 GPIO[43] gpio 43 GPIO[44] gpio 44 GPIO[45] gpio 45 GPIO[46] gpio 46 GPIO[47] gpio 47 GPIO[48] gpio 48 GPIO[49] mem_addr_19 GPIO[50] mem_addr_20 GPIO[51] gpio 51 GPIO[52] gpio 52 GPIO[53] gpio 53 GPIO[54] gpio 54 GPIO[55] gpio 55 GPIO[56] gpio 56 GPIO[57] gpio 57 GPIO[58] gpio 58 GPIO[59] gpio 59 GPIO[60] gpio 60 GPIO[61] gpio 61 GPIO[62] gpio 62 GPIO[63] gpio 63
iomx validate sample output with duplicated pin configurations:
DMON > iomx validate GPIO[00] mem_addr_0 GPIO[01] mem_addr_1 GPIO[02] mem_addr_2 GPIO[03] mem_addr_3 GPIO[04] mem_addr_4 GPIO[05] mem_addr_5 GPIO[06] mem_addr_6 GPIO[07] mem_addr_7 GPIO[08] mem_addr_8 GPIO[09] mem_addr_9 GPIO[10] mem_addr_10 GPIO[11] mem_addr_11 GPIO[12] mem_addr_12 GPIO[13] can_tx_0 GPIO[14] can_rx_0 GPIO[15] can_en_0 GPIO[16] mem_addr_16 GPIO[17] mem_addr_17 GPIO[18] mem_addr_18 GPIO[19] ram_csn_0 GPIO[20] gpio 20 GPIO[21] gpio 21 GPIO[22] gpio 22 GPIO[23] gpio 23 GPIO[24] gpio 24 GPIO[25] mem_data_0 GPIO[26] mem_data_1 GPIO[27] mem_data_2 GPIO[28] mem_data_3 GPIO[29] mem_data_4 GPIO[30] mem_data_5 GPIO[31] mem_data_6 GPIO[32] mem_data_7 GPIO[33] mem_oen GPIO[34] mem_wrn GPIO[35] gpio 35 GPIO[36] gpio 36 GPIO[37] can_tx_0 Already mapped GPIO[38] can_rx_0 Already mapped GPIO[39] can_en_0 Already mapped GPIO[40] gpio 40 GPIO[41] gpio 41 GPIO[42] gpio 42 GPIO[43] gpio 43 GPIO[44] gpio 44 GPIO[45] gpio 45 GPIO[46] gpio 46 GPIO[47] gpio 47 GPIO[48] gpio 48 GPIO[49] mem_addr_19 GPIO[50] mem_addr_20 GPIO[51] gpio 51 GPIO[52] gpio 52 GPIO[53] gpio 53 GPIO[54] gpio 54 GPIO[55] gpio 55 GPIO[56] gpio 56 GPIO[57] gpio 57 GPIO[58] gpio 58 GPIO[59] gpio 59 GPIO[60] gpio 60 GPIO[61] gpio 61 GPIO[62] gpio 62 GPIO[63] gpio 63
Memory Protection
The GR716 microcontroller has 2 separate AMBA memory protection units (MEMPROT). The MEMPROT units have the capability to detect and protect memory areas from write accesses. The first memory protection unit (MEMPROT0) is connected to Main AHB bus and the second memory protection unit (MEMPROT1) is connected to the DMA AMBA bus. Each memory protection unit has a unique address for configuration and status. The control and status registers for the memory protection units are located on APB bus in the address range 0x80005000 to 0x80005FFF 0x8010A000 to 0x8010AFFF.
DMON provides the commands below to configure memory protection.
Command | Description |
---|---|
mprot reg | Show GRMEMPRO registers |
mprot set [n][saddr][eaddr][none|all|g0-g15..] | Protect area [seg num][s address][e address][none|all or array of g0-g15] |
Memory Protection Device View
Memory Protection Device View (enabled)
Clock Gating options
The GR716 microcontroller have 2 separate clock gating units. Each clock gating unit will control its own clock domains and have a unique AMBA address.
The clock gating units provide a means to save power by disabling the clock to unused functional blocks. These cores provide a mechanism to automatically disable the clock to LEON processors in power-down mode, and optionally also to disable the clock for shared floating-point units. The cores also provide a mechanism to reset, enable clock and disable clocks for most functional blocks.
Command | Description |
---|---|
grcg [enable|disable][all|bit..bitN] | Enable|Disable all, single bit or array of bits for GRCLKGATE_0 |
-grcg [enable|disable][all|bit..bitN] | Switch to Enable|Disable all, single bit or array of bits for GRCLKGATE_0 or -grcg_1 for GRCLKGATE_1, at DMON start up |
grcg reg | Show register values for GRCLKGATE_0 |
Commands
The table below is a summary of commands specific to the GR716.
Command | Description |
---|---|
breakrexs [addr]<cpuID> | Force to set REX Software break point. breaks command will scan if address is in REX block and set REX software break point |
coderex [addr]<length> <force> | Disassemble REX instructions in memory. DMON will detect if address is in REX block and disassemble as REX. Force switch will bypass detection and disassemble as REX instruction |
dlram edac [enable|disable] | Enable|Disable EDAC |
dlram scrub [enable|disable] | Enable|Disable Scruber |
gpio pulse status | Show Pulse register for GRGPIO |
gradcdac config | Display status information for the GRADCDAC core |
grcan [enable|disable] | Enable|Disable the GRCAN receiver |
grcan reset | Resets the GRCAN receiver |
grcan status | Show register values for GRCAN |
grcg [enable|disable][all|bit..bitN] | Enable|Disable all, single bit or array of bits for GRCLKGATE_0 |
grcg reg | Show register values for GRCLKGATE_0 |
grdmac_0 b2m add [data|cond|econd] ch[N][addr] | Create B2M data|conditional|extended conditional descriptors at address for Channel |
grdmac_0 b2m remove [data|cond|econd] ch[N] [addr] | Remove B2M descriptor at address for Channel |
grdmac_0 core [en|dis] | Enable(Run) or Disable(Stop) GRDMAC Core |
grdmac_0 core reset | Reset GRDMAC Core to default values |
grdmac_0 ctrl ie [en|dis] | Global Interrupt Enable or Disable |
grdmac_0 ctrl iee [en|dis] | Interrupt Enable or Disable for Errors |
grdmac_0 ctrl me [en|dis] | Extended Mode Enable or Disable |
grdmac_0 ctrl ns [en|dis] | No Starve Mode Enable or Disable |
grdmac_0 ctrl sm [en|dis] | Simplified mode Enable or Disable |
grdmac_0 ctrl te [en|dis] | Timer Enable or Disable |
grdmac_0 ech [en|dis][all|ch# ch#+1] | Set Channel/Channels/All Channels Enabled/Disabled |
grdmac_0 ech [en|dis][ch#-ch#+n] | Set Channel Enabled or Disabled for Range of Channels |
grdmac_0 eirq [en|dis] | Set Interrupt enable for Errors (IEE) |
grdmac_0 error reset | Reset Error Register |
grdmac_0 irq [en|dis] | Set GRDMAC Global Interrupt Enable or Disable (IE) |
grdmac_0 irq [en|dis][all|ch# ch#+1] | Set Interrupt Mask for Channel/Channels/All Channels and Enable Global IRQ |
grdmac_0 irq [en|dis][ch#-ch#+n] | Set Interrupt Mask for Range of Channels and Enable Global IRQ |
grdmac_0 irq reset | Reset Interrupt Flag Register for all channels |
grdmac_0 load [file] | Load GRDMAC configurations from XML file |
grdmac_0 m2b add [data|cond|econd] ch[N] [addr] | Create M2B data|conditional|extended conditional descriptors at address for Channel |
grdmac_0 m2b remove [data|cond|econd] ch[N] [addr] | Remove M2B descriptor at address for Channel |
grdmac_0 save [file] | Save GRDMAC configuration to XML file |
grdmac_0 sbufdata | Display Internal Buffer Readout Area |
grdmac_0 scan | Scan M2B and B2M descriptor linked lists using Channel Vector Pointer |
grdmac_0 sdata [addr] | Print DMA data after successful B2M Descriptor at address |
grdmac_0 set cvp [value] | Set Channel Vector Pointer (CVP) |
grdmac_0 set trv [value] | Set Timer Reset Value (TIMER_RST) |
grdmac_0 status [offset] | Display GRDMAC core status of All registers or at offset (i.e.0x04) to the screen |
grdmac_0 tsl [0|32|64|128] | Set Transfer Size limit (TSL) |
grpwm <dev#> enable|disable | Enable or Disable the GRPWM core |
grpwm <dev#> status | Display status information for the GRPWM core |
grpwrx [enable|disable] | Enable|Disable the GRPWRX reciever |
grpwrx dma [enable|disable] | GRPWRX dma Enable|Disable |
grpwrx reset | Resets the GRPWRX reciever |
grpwrx status | Show register values for GRPWRX |
grpwtx [enable|disable] | Enable|Disable the GRPWTX reciever |
grpwtx dma [enable|disable] | GRPWTX DMA Enable|Disable |
grpwtx reset | Resets the GRPWTX Transmitter |
grpwtx status | Show register values for GRPWTX |
i2c2ahb enable|disable | Enable or Disable the I2C2AHB core |
i2c2ahb irq enable|disable | Display status information for the I2C2AHB core |
i2c2ahb status | Display status information for the I2C2AHB core |
ilram edac [enable|disable] | Enable|Disable EDAC |
ilram scrub [enable|disable] | Enable|Disable Scruber |
iomx set [configName configName ...] | Set IOMX configurations for Device or Array of Devices |
iomx setpin [gpioN][val] | Set IOMX GPIO pin to value |
iomx show <all|configName> | Display all available IOMX configurations or Search by prefix |
iomx validate | Validate IOMX configurations |
mprot reg | Show GRMEMPRO registers |
mprot set [n][saddr][eaddr][none|all|g0-g15..] | Protect area [seg num][s address][e address][none|all or array of g0-g15] |
rex [en|ill|tr]<cpuID> | Sets the REX mode(enable|illegal|transparent) for active cpu or cpuID if provided |
spi2ahb enable|disable | Enable or Disable the SPI2AHB core |
spi2ahb irq enable|disable | Enable or disable interrupts for SPI2AHB core |
spi2ahb status | Display status information for the SPI2AHB core |
spislave status | Show registers values for SPI4SPACE |
spislave reset | Reset SPI4SPACE device |
spim edac <enabled|disable> | Enable or Disable EDAC in SPIMCTRL |
spwtdp status | Display status information for the SPWTDP core |